1. Field of the Invention
This invention generally relates to television receivers and particularly to an improvement of a television receiver provided with a field memory capable of storing video signals of one field. More particularly, this invention relates to a construction of a television receiver capable of storing desired video signals in one field and reproducing the stored video signals of one field as a still image on a television receiver as required.
2. Description of the Prior Art
Recent developments in semiconductor technologies have led to the realization of large-capacity memories and high-speed analog-to-digital (A/D) converters, making possible digital image processing. Examples of devices used in such digital image processing are field memories. Such a field memory is capable of receiving and storing A/D converted video signals for one image (corresponding to one field) on a television screen. FIG. 1 shows a flow of a video signal in the case of using a field memory.
Referring to FIG. 1, an analog video signal is sampled in an A/D converter 1 at a predetermined frequency and converted to a digital video signal. The digital video signal from the A/D converter 1 is supplied to a field memory 2, where it is stored. The field memory 2 stores pixel information for one field. The pixel information (the digital video signal) stored in the field memory 2 is successively read out in the order of storing, so as to be supplied to a digital-to-analog (D/A) converter 3. The D/A converter 3 converts the digital video signal to an analog video signal and supplies it to a succeeding signal processing circuit (e.g., a video amplifier). A serial access memory having a construction as shown in FIG. 2 is generally used as the field memory 2.
Referring to FIG. 2, the serial access memory includes a memory cell array 10 for storing pixel information for one field. The memory cell array 10 includes memory cells arranged in a matrix comprising rows and columns. The number of memory cells (i.e., a memory capacity) is determined dependent on a sampling frequency for conversion from an analog signal to a digital signal (i.e., the number of pixels in one field).
In order to select a row in the memory cell array 10, there are provided an address counter 11 for providing a row address, an address buffer 12 for accepting the row address from the address counter 11 and providing an internal row address, and an address decoder 13 for decoding the internal row address from the address buffer 12 to select a corresponding row of the memory cell array 10. The address counter 11 increments the row address by one in response to a signal INC and decrements the row address by one in response to a signal DEC. The row address is reset in response to a signal RCR. Thus, it becomes possible to select corresponding rows successively from the memory cell array 10 one by one or by skipping by a predetermined number of rows.
In order to write pixel information into the memory cell array 10 and to read out the stored pixel information, there are provided a data transfer gate 15 to be turned on in response to a timing signal from a read/write timing generating circuit 14, a line buffer 16 for latching data for one row of the memory cell array 10, a serial selector 17 for determining speeds of writing and reading of data, and a Y gate 18 for successively connecting each latch portion of the line buffer 16 to a data input/output buffer 19 in response to an output of the serial selector 17. The serial selector 17 is activated in response to a timing signal from a timing generating circuit 20 to successively turn on gate transistors of the Y gate 18 in response to a timing signal from a serial control timing generating circuit 21.
The timing generating circuit 20 generates various timing signals in response to a signal RAS.
The read/write timing generating circuit 14 generates timing signals for reading and writing of data in response to a signal WE.
The serial control timing generating circuit 21 is enabled in response to the timing signal from the read/write timing generating circuit 14 to generate a signal synchronized with a shift signal SC and to apply serial transfer timing for data.
The data input/output buffer 19 serially transfers input data D.sub.IN and output data D.sub.OUT in response to a control signal from the serial control timing generating circuit 21.
Pixel data for one horizontal scanning line on a television screen are stored in memory cells of one row as shown in FIG. 3. Accordingly, a distribution of pixel data on the television screen corresponds to a distribution of pixel data in the memory cell array 10 with a relation of 1:1 correspondence.
Now, operation of the field memory will be briefly described.
1. Serial write cycle
As shown in FIG. 4, this cycle is executed when the signal WE is changed to low (L) level at the time of input of the signal SC. Data is accepted by the input/output buffer 19 at a falling edge of the signal SC. The data thus accepted is transferred to the line buffer 16 through the Y gate 18 under control of the serial selector 17, so that it is latched in the line buffer 16. At that time, the written data can be outputted.
2. Serial read cycle
In this cycle, the data latched in the line buffer 16 are read out through the Y gate 18 and the data input/output buffer 19 at a falling edge of the signal SC when the signal WE is at high (H) level, as shown in FIG. 5.
3. Data restore cycle
In this cycle, the data for one row latched in the line buffer 16 are simultaneously written in a selected row in the memory cell array 10. This cycle is executed by opening the data transfer gate 15 when the signal WE is at L level at a fall of the signal RAS, as shown in FIG. 6. At that time, a row is selected based on the row address from the address counter 11.
4. Data transfer cycle
In this cycle, data for a selected row in the memory cell array 10 are transferred to the line buffer 16. This cycle is executed when the signal WE is at H level at a fall of the signal RAS, as shown in FIG. 7.
5. Row address counter cycle
In this cycle, a row address to be provided by the address counter 11 is defined. This cycle is executed when any one of the signals INC, DEC and RCR is at L level with the signal RAS being at H level. Control of the field memory is performed by changing the signal INC to L level for each horizontal scanning line (that is, in response to a horizontal synchronizing signal) and by inputting the signal RCR for each vertical scanning period.
Such a field memory as described above is widely utilized in various digital image processing technologies. An example of application of such a field memory is a so-called digital television receiver (for example as indicated in the technical journal "Television Technology" '84 Dec. Issue, pp. 31-37).
Such a conventional digital television receiver using a field memory has a picture-in-picture function for displaying two screens on a television screen and a still image display function for temporarily stopping a moving image to represent it to as a still image, and other functions.
The picture-in-picture function is to display two screens V1 and V2, i.e., the larger screen V1 and the smaller screen V2 in a multiple manner on the television screen. The picture-in-picture function also includes a function of displaying a still image on the scaled-down screen V2. FIG. 10 schematically shows a construction of a digital television receiver having the picture-in-picture function.
Referring to FIG. 10, signal processing is performed through two paths.
The first path is a signal processing path for display of a sub screen (a scaled-down screen). This path includes: a signal processing circuit 31 for receiving an analog video signal from a sub screen video signal input terminal 30 and performing necessary processing for the signal; a timing pulse generator 32 for providing various timing signals (clocks) based on horizontal and vertical synchronizing signals detected by the signal processing circuit 31; and a memory controller 34 responsive to the clock from the timing pulse generator 32, for controlling writing and reading of pixel data for a field memory 33. An A/D converter 35 for sampling the analog signal in response to the clock from the memory controller 34 is provided between the signal processing circuit 31 and the field memory 33.
The signal processing circuit 31 provides a luminance signal Y and color-difference signals R-Y and B-Y by YC separation of the input analog video signal and also detects the horizontal synchronizing signal and the vertical synchronizing signal. The memory controller 34 provides various control signals shown in FIG. 2.
The second processing path is a main screen display path, which includes an A/D converter 36 for sampling an analog signal from a main screen video signal input terminal 50 at a predetermined sampling rate, and a digital signal processing circuit 37 for performing predetermined processing for an output of the A/D converter 36.
The digital signal processing circuit 37 performs signal processing, similar to that in the signal processing circuit 31, in a digital manner. Horizontal and vertical synchronizing signals detected by the digital signal processing circuit 37 are supplied to the memory controller 34.
A screen display path includes: a multiplexer 38 for selectively passing either an output of the field memory 33 or an output of the digital signal processing circuit 37; a D/A converter 39 for converting an output of the multiplexer 38 to an analog signal; a video amplifier 40 for receiving an output of the D/A converter 38 and providing color signals R, G and B; and a CRT 41 for displaying a corresponding image in response to an output of the video amplifier 40.
The multiplexer 38 selects either sub screen data or main screen data to pass therethrough under control of the main controller 34. As a result, it is made possible to represent a sub screen in a scaled-down manner at a predetermined position in the main screen. The scaled-down display of the sub screen is realized by increase of a data reading speed from the field memory 33 and suitable skipping of row addresses.
During the sub screen display operation, the video signal from the input terminal 30 is written in the field memory 33 and it is read out therefrom in synchronization with the main screen, so that it is supplied to the multiplexer 38. The multiplexer 38 provides, under control of the memory controller 34, image information including the sub screen video signal inserted in a main screen video signal.
During the still image display operation, writing of data in the field memory 33 is inhibited and video data for one field stored in the field memory 33 is repeatedly read out and supplied to the multiplexer 38. Thus, the image data for one field in the field memory 33 is repeatedly reproduced at a predetermined position in the main screen and, thus, a still image is obtained.
The above described still image display can be made also in the case of displaying only the main screen and, in addition, a desired scene can be fixed as a still image and displayed on the sub screen.
Accordingly, the conventional still image display function enables an image currently displayed to be still and displayed on the television screen in response to a still image instruction signal.
However, according to the conventional still image function, if the display of the still image is cancelled or completed, new video signals are written in the field memory and read out. More specifically, the still image information displayed till then is updated with new different image information. Therefore, the still image displayed previously cannot be displayed again on the television screen.
On the other hand, there are some television programs in which a large amount of information is displayed at a time in a short period, such as a program of cooking in which materials used for cooking are simultaneously displayed in the form of letter information or a weather forecast for all parts of the country. In those cases, if one wants to have exact knowledge of the information by temporarily storing the image including the information and reproducing it afterwards to thoroughly observe it, it is not possible in the conventional digital television receiver having the still image display function to reproduce again the still image once the display of the still image has been cancelled or completed.
Thus, the conventional digital television receivers make no allowance for construction for temporarily storing television image information and reproducing afterwards the stored image as required.